volatile Keyword
Tells the Compiler that a variable's value can change at any time - without any action from the code itself.
Compiler Logic
Control: Optimization
Basic Concept
Prevents the compiler from Caching values in CPU registers for
speed.
Mechanism
Forces every read/write to access the memory location as defined, preventing
register caching.
Usage Context
Context: Synchronization
Basic Concept
Synchronizes software with external events.
Primary Targets
Hardware Registers, ISR-shared variables, and polling
flags.
The Silicon Reason
Hardware Interaction
In Silicon, a peripheral status register may change
asynchronously due to events such as UART data reception or a
timer expiry.
The Reason
The compiler only sees C Code and cannot know that
Hardware or Interrupts may modify memory independently of
the program’s execution.